Samsung Unveils Three-Phase HBM Roadmap Merging Memory and Compute

Samsung’s HBM Roadmap Announcement

At Hot Chips 2026, Samsung announced a three-phase technical roadmap for HBM (High Bandwidth Memory). Explained by Sangwook Han of the company’s DRAM design team, the roadmap envisions progressively merging the boundary between memory and compute by introducing advanced logic processes to the base die.

The final stage, dubbed zHBM, involves positioning the processor directly beneath the DRAM stack, eliminating the conventional 2.5D interposer connection. According to a report by Tom’s Hardware’s Etiido Uko, Samsung positions the base die as the key enabling this evolution.

Current HBM Structure and Challenges

The current HBM architecture vertically stacks multiple DRAM core dies atop a base die, connected via TSVs (Through-Silicon Vias). The stack is placed on an interposer adjacent to the XPU (compute chips like GPUs and AI accelerators), with the base die acting as a bridge between memory and compute silicon.

Expanding bandwidth has been the primary driver of HBM evolution. Current HBM4 stacks feature 1,000 to 2,000 I/Os, each operating at 8 to 16 Gbps, achieving a total bandwidth of 1 to 5 TB/s. However, conventional bandwidth scaling methods have accumulated several structural challenges.

Improving TSV signal speed is physically difficult, leading to an increase in the number of TSVs with each HBM generation. This consumes die area and necessitates tighter TSV pitch. PHY circuits have also continued to expand; HBM4 doubled the data I/O count to 1,024–2,048 DQs, and the resulting increase in circuit scale is significant.

Power consumption is an even more critical issue. While energy efficiency per bit is improving, total power consumption fails to keep pace with bandwidth scaling and continues to rise. Samsung explains that this power issue is the rationale for requiring a process change for the base die in the HBM4 generation.

Transition to Logic Process for the Base Die

To address these power and area challenges, Samsung changed the manufacturing process for the base die in HBM4 from the traditional DRAM process to an advanced logic process. Specifically, using a 4nm logic process for the base die achieves reduced power consumption and die area.

A more significant point is that a base die built with the same class of logic process as the XPU can serve functions beyond a mere data interface. Being manufactured with the same logic process as the XPU opens the possibility of integrating compute or data processing functions directly onto the base die. Samsung refers to this direction as cHBM (custom HBM) and positions it as the first phase of the roadmap.

This approach changes the framework where HBM was previously viewed as a “memory technology.” The base die being manufactured with a logic process begins to merge the technological domains of memory vendors and logic foundries.

The Three-Phase Roadmap

Samsung’s roadmap consists of three stages.

The first phase is cHBM (custom HBM). It maintains the conventional DRAM stack configuration while customizing the logic circuits of the base die for specific applications. By offloading some data transformation and preprocessing tasks from the processor to the base die, it alleviates communication bottlenecks via the interposer. The base die remains positioned beneath the DRAM stack, but its circuits evolve from a generic interface to custom logic.

The second phase involves further functional integration into the base die. Details on the stage beyond cHBM were discussed in the Hot Chips 2026 presentation materials, suggesting a direction where the scale and functionality of the logic integrated onto the base die expand.

The third phase is zHBM. In this stage, the processor is positioned directly beneath the DRAM stack. The conventional 2.5D interposer is eliminated, removing the physical gap between the DRAM and XPU. Tom’s Hardware’s article explains this integrates memory and compute into a single vertical stack.

Technical Significance of zHBM

Realizing zHBM has the potential to significantly reduce the latency and power consumption of inter-chip communication. Eliminating the interposer as an intermediate layer shortens the signal transmission distance and is expected to improve energy efficiency.

In conventional 2.5D packaging, the memory stack and XPU are co-located on an interposer, with data exchanged through the base die. In this structure, data incurs latency and energy costs when traversing the interposer. In zHBM, this intermediate layer is gone, and the TSVs of the DRAM stack connect directly to the processor.

As the performance improvement of AI and HPC becomes increasingly dependent on memory bandwidth, Samsung’s roadmap represents an attempt to redefine the very boundary between memory and compute. Ahead of developments like Linux 7.2-rc1 release integrating AMDGPU HDMI 2.1 FRL and Cache Aware Scheduling, such hardware architectural changes are anticipated to emerge.

Industry Impact and Challenges

Samsung’s announcement could impact the competitive landscape of the HBM market. With SK Hynix currently holding a market share advantage, Samsung appears to be positioning the convergence of packaging and foundry technology as a differentiating factor.

The policy of manufacturing the base die with a logic process leverages Samsung’s structure as a conglomerate. It can be inferred that this aims to strengthen its position in the HBM value chain by fostering collaboration between its foundry and DRAM businesses.

However, realizing zHBM faces numerous technical hurdles. Thermal management is one of the most prominent issues. Placing the processor directly beneath the DRAM stack concentrates heat sources vertically, requiring more effective cooling solutions than before. Mechanical reliability between dies and stress management when integrating dies of different processes into the same package are also challenges to be overcome.

Editorial Opinion

Samsung’s announcement expands its existing plan to transition the base die to a 4nm logic process in the HBM4 generation. In the next 3-6 months, attention will be on what counter-roadmaps competitors introduce. How far SK Hynix and Micron pursue similar packaging innovations will likely determine the competition in the HBM market. The customizability in the cHBM phase could provide new options for various AI chip designers. If zHBM commercialization progresses, the very premise of chiplet architectures could change. With DRAM and the processor integrated in a single stack, the design philosophy of the memory hierarchy would be fundamentally re-examined. As latency requirements in AI inference tighten, eliminating the interposer will significantly impact overall system power efficiency. Looking at a 1-3 year horizon, this type of integrated architecture could proliferate in both edge AI and data centers. Samsung has not disclosed specific performance metrics for the extent of compute functions that can be integrated onto the logic-process base die.

References

• ” Hot Chips 2026: Samsung reveals a three-phase HBM roadmap that puts logic and compute inside memory — zHBM ultimately stacks DRAM directly on top of the processor ”, by Etiido Uko — Tom’s Hardware, 2026-09-01T11:06:15.000Z (ARR)
• Source URL: https://www.tomshardware.com/tech-industry/semiconductors/hot-chips-2026-samsung-reveals-a-three-phase-hbm-roadmap-that-puts-logic-and-compute-inside-memory-zhbm-ultimately-stacks-dram-directly-on-top-of-the-processor