NVIDIA GPUs Pack 10-40 RISC-V Cores for Control Tasks
Each NVIDIA GPU includes 10-40 RISC-V cores for non-graphics control. Explaining the transition from Falcon.
Each NVIDIA GPU includes 10-40 RISC-V cores for non-graphics control. Explaining the transition from Falcon.
An engineer's systematic critique of RISC-V's ISA design: contradictions in its universal-use philosophy and chip implementation challenges.
RISC-V is a free, open-source processor instruction set architecture. This article comprehensively explains its features compared to x86 and ARM, advantages and disadvantages, a wide range of real-world applications from embedded systems to servers, and the latest industry trends.
Tenstorrent has published GCC patches for the RISC-V core Ascalon XG. Export variant with reduced cryptographic extensions may be emerging.
GNU Binutils 2.47 has been released, supporting numerous RISC-V extensions and adding optimized linking options, promising reduced build times.
Linux 7.2-rc3 has been released, featuring Ultra RISC-V support, Dreamcast driver fixes, and numerous AI-assisted patches. Linus Torvalds hints at a transition to a "new normal." Ubuntu 26.10 will also adopt this kernel.
UltraRISC support has been integrated into Linux 7.2's RISC-V defconfig, targeting the UR-DP1000 SoC (8-core C100), expanding the ecosystem.
Pine64 releases the PineVoice smart speaker with a RISC-V processor for $50. Built on Home Assistant and privacy-focused, but lacks wake word detection.
The Linux Kernel 7.2 integrates around 1,000 SoC-related patches. Five new SoCs, including Apple M3 and Qualcomm Dragonwing IPQ9650, are now supported in the mainline kernel, along with added support for Microsoft Surface Pro 12.