Intel Xeon 7 Diamond Rapids Features 256 Cores and 1.28TB Cache

Up to 256 Cores and 1.28TB Cache

At Hot Chips 2026, Intel unveiled technical details for the first time regarding its next-generation server processor, the “Xeon 7.” Codenamed “Diamond Rapids,” this new lineup will feature up to 256 P-cores and 1.28TB of last-level cache and is slated for the data center market in 2027.

According to a report by Jake Roach of Tom’s Hardware, Diamond Rapids employs Intel’s latest process technology, “18A-P,” and introduces the UCIe-S interconnect, the AVX 10.2 instruction set, and a new disaggregated fabric. The core architecture itself is codenamed “Panther Cove,” though details were not revealed at Hot Chips 2026.

Constructed with Compute Building Blocks

The most significant technical feature of Diamond Rapids lies in its Compute Building Blocks (CBBs). Each CBB contains up to four core chiplets, with each chiplet housing 16 P-cores. By integrating four CBBs, a total of up to 256 cores is achieved.

Each core has a private L2 cache within its chiplet and accesses a shared L3 cache set on the base tile. The connection between the chiplets and base tiles uses a 3D Crossbar (3D Xbar), to which Intel’s Foveros Direct 3D packaging technology is applied.

The overall SoC configuration for Diamond Rapids is as follows: Four base tiles are manufactured on the Intel 3-T process, two fabric hub tiles on the Intel 3 process, and 16 core chiplets on the Intel 18A-P process.

Transition to UCIe-S and Abandonment of EMIB

Notably, Intel has decided not to use EMIB (Embedded Multi-die Interconnect Bridge), a technology it has widely deployed in the past, for Diamond Rapids. Instead, the UCIe-S interconnect is used to connect the CBBs and fabric hub tiles. Core-to-cache communication occurs via 2D pathways.

Each CBB connects to both fabric hubs, ensuring efficient communication paths across the entire chip. Compared to Granite Rapids, the layout in Diamond Rapids is inverted: memory and I/O are consolidated in the center, while the cores are positioned on the periphery.

Continued Use of Foveros Direct 3D

Similar to the Xeon 6+ “Clearwater Forest,” Diamond Rapids continues to use 3D packaging via Foveros Direct 3D. This creates a hybrid configuration where 3D packaging binds chiplets and base tiles within each CBB, while 2D UCIe-S is used for inter-CBB connections.

The adoption of the 18A-P process is significant in Intel’s process roadmap. It is considered one of the key implementations to gauge whether Intel’s manufacturing technology is regaining competitiveness against rivals.

Editorial Opinion

Short-term Impact: The revelation of Diamond Rapids underscores Intel’s renewed presence in the server CPU market. The figure of up to 256 cores serves as a clear counter to AMD’s EPYC series. Specific performance benchmarks and pricing strategies will attract market attention as the 2027 launch approaches. The manufacturing capacity of the 18A-P process is expected to be the core factor determining this product’s competitiveness. Long-term Perspective: The transition from EMIB to UCIe-S can be evaluated as a turning point in Intel’s packaging strategy. Adopting the industry-standard UCIe could facilitate collaboration with third parties and contribute to ecosystem expansion. The inversely designed architecture is likely to enhance flexibility for future chiplet designs and ease the development of next-generation processors. Editorial Question: Will the software ecosystem capable of fully utilizing 256 cores be ready by 2027?

References

• ” Intel Xeon 7 ‘Diamond Rapids’ comes with up to 256 P-cores, 1.28 GB of last-level cache — next-gen 18A-P CPU also brings AVX 10.2 and uses UCIe-S instead of EMIB ”, by Jake Roach — Tom’s Hardware, 2026-08-24T21:07:45.000Z (ARR)
• Source URL: https://www.tomshardware.com/pc-components/cpus/intel-xeon-7-diamond-rapids-comes-with-up-to-256-p-cores-1-28-gb-of-last-level-cache-next-gen-18a-p-cpu-also-brings-avx-10-2-and-uses-ucie-s-instead-of-emib