Criticism of RISC-V: Engineer Points Out Contradictions in ISA Design
An engineer's systematic critique of RISC-V's ISA design: contradictions in its universal-use philosophy and chip implementation challenges.
Main text:
RISC-V is rapidly gaining adoption as an “open ISA that anyone can use.” On August 14, 2026, engineer dmitrygr posted a lengthy critical article titled “RISC-V: They Should Have Known Better” on Lobsters. The article systematically points out contradictions inherent in RISC-V’s design philosophy and is attracting attention in the technical community.
The Contradiction of Claiming to Cover All
Use Cases
The first point dmitrygr raises is RISC-V’s very claim of being “optimal for all use cases.” The assertion that a single ISA can deliver an optimal solution for everything from supercomputers to tiny microcontrollers is unrealistic. The performance characteristics demanded by high-end CPUs are fundamentally at odds with those required by small microcontroller cores focused on cost reduction. This is not merely a matter of microarchitecture; it is a design-choice problem that affects the CPU architecture itself.
RISC-V fans would have you believe that RISC-V will soon own all supercomputers, while also owning all the tiny microcontroller use cases, and all things in between. This is impossible, and would be equally impossible for any ISA.
The article explicitly states that this problem applies not only to RISC-V but to all ISAs. It should be read not as an emotional attack on a particular ISA, but as structural skepticism toward design principles.
The Real Demands of Low-Cost Microcontrollers
The article analyzes the specific requirements of inexpensive one-time microcontrollers. In products such as MP3 players, SD cards, and USB flash drives, custom IP handles the main processing, and the CPU core merely performs temporary writes to registers or reconfigures hardware blocks. The key metrics for this use case are interrupt latency (lower is better) and chip area (smaller is better).
In mass-produced devices where cost reduction is pursued to the extreme, code is executed from ROM or RAM. NOR flash is too expensive, so it is ruled out. When executing from ROM, code compactness directly translates to ROM area. Even when executing from RAM, SRAM occupies a large area on the die, so code density remains an important design metric.
Since mathematical operations are assumed to be minimal, hardware dividers and multipliers are deemed unnecessary. In such environments, an ISA’s rich set of extension instructions is nothing more than overhead.
Optional Design and Structural Gaps
From the article’s table of contents, it is clear that dmitrygr also addresses the following topics: “Optionality” examines the problem of RISC-V providing an excessive number of optional extension instructions; “Missing Obvious Pieces” addresses design elements that should exist but are absent; and “Ridiculous encoding” takes up problems with the instruction encoding scheme.
RISC-V’s extension instruction design is intended to support a wide variety of use cases while maintaining compatibility. However, dmitrygr criticizes this optional design philosophy itself for leading to implementation complexity and compatibility issues.
Current Status and Future Outlook
At the end of the article, dmitrygr includes a section titled “Does This Mean RISC-V is Doomed?” and offers a certain degree of praise in his conclusion. As he himself acknowledges at the beginning of the article, RISC-V will capture the ultra-low-cost microcontroller market as the successor to the 8051. This is not because of the excellence of its ISA design, but because the 8051 was a target that had only ever set a low bar.
RISC-V will own the cheap-as-dirt single-use microcontroller space eventually. Not due to its ISA design, but despite it.
The core insight the article suggests is that the value of being an open ISA and the technical quality of the ISA design itself are separate matters. RISC-V’s commercial success depends on its open-source ecosystem and the low barriers to entry for chip vendors, and should be discussed independently of the technical superiority of the instruction set architecture itself.
Editorial Opinion
In the short term, this critical article is likely to prompt a reexamination of design philosophy within the RISC-V ecosystem. In particular, as RISC-V International proceeds with developing the next specifications, it could influence reviews of the optional design of extension instructions and encoding. Whether the semiconductor companies currently adopting RISC-V cores will treat this as a concern regarding long-term ISA stability remains an open question.
In the long term, the focus will be on whether RISC-V’s design weaknesses affect market choices as ISA-level competition with x86 and ARM intensifies. In high-end server and high-performance computing fields, ISA design quality can be a differentiating factor. In the embedded market, by contrast, cost and openness are overwhelmingly important, and the aesthetic perfection of an ISA is a secondary concern.
The fundamental question this article raises is that being open does not necessarily mean being technically best. The tendency to equate “open” with “optimal” is a cognitive trap seen not only with RISC-V but throughout open-source software in general.
References
- “RISC-V: They Should Have Known Better”, by dmitry.gr by dmitrygr — Lobsters, 2026-08-14T19:12:53.000Z (ARR)
- Source URL: https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV
Frequently Asked Questions
- What is the main criticism of RISC-V's design philosophy?
- dmitrygr fundamentally takes issue with RISC-V's positioning as "optimal for all use cases," from supercomputers to ultra-low-cost microcontrollers. He argues that the demands of high-end CPUs and low-cost microcontrollers are essentially at odds, and that a design philosophy attempting to satisfy both with a single ISA contains inherent contradictions.
- Will this critical article affect RISC-V's adoption?
- The article itself does not deny RISC-V's adoption prospects. It acknowledges that RISC-V will replace the existing 8051 in the ultra-low-cost microcontroller market. However, the observation that design quality can influence ISA selection for supercomputers and high-end applications may affect the future development of RISC-V extension specifications.
- What is the "code density" problem mentioned in the article?
- In low-cost mass-produced devices, the area of ROM and SRAM is directly tied to cost, so the size of binary code stored in memory matters. The criticism that RISC-V's instruction encoding is not sufficiently optimized from this perspective is developed in the article's "Ridiculous encoding" section.
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