What is RISC-V? Differences from x86/ARM and Latest Trends

Basic Concepts of RISC-V

RISC-V is an open-source instruction set architecture whose development began in 2010 at the University of California, Berkeley. In conventional processor development, proprietary instruction sets whose licenses were monopolized by specific companies—such as Intel’s x86 or ARM’s architecture—were the mainstream. RISC-V transformed this historical structure, designed as a specification that anyone can use for free and extend independently.

An instruction set architecture (ISA) is the basic set of instructions executed by a processor, defining the interface between hardware and software. RISC-V follows the principles of RISC (Reduced Instruction Set Computer), adopting a simple and efficient instruction set. The length of base instructions is fixed, making decoding easier.

Today, this technology is managed and standardized by the nonprofit organization “RISC-V International.” Major tech companies such as Google, Samsung, NVIDIA, and Huawei, along with numerous universities and research institutions, participate in this organization, and the formation of its ecosystem is advancing rapidly.

Architectural Features of RISC-V

RISC-V’s design philosophy is encapsulated in modularity and extensibility. The specification is divided into the “base instruction set” and “extended instruction sets,” allowing only the necessary elements to be combined according to the application.

The base instruction sets include “RV32I” with 32-bit instruction length and “RV64I” with 64-bit instruction length. In addition, standard extensions are defined, such as the “M” extension for multiplication and division, the “A” extension for atomic instructions, the “F” and “D” extensions for single- and double-precision floating-point operations, and the “C” extension for 16-bit compression. Furthermore, custom extensions for vector operations, cryptographic processing, and other purposes can be added independently.

The register architecture is also distinctive. It has 32 general-purpose registers (x0–x31), and the x0 register always returns a zero value. This design contributes to instruction efficiency and simplifies decoding. The privilege model is also clearly defined, supporting machine monitor mode, supervisor mode, and user mode.

Comparison with x86 and ARM

The main differences among x86, ARM, and RISC-V can be summarized in three points: technical philosophy, cost structure, and barriers to entry.

x86 is based on CISC (Complex Instruction Set Computer) and is effectively an oligopoly held by two companies, Intel and AMD. It offers high performance, but processor design requires cross-licensing, and entry costs are extremely high. ARM is RISC-based and requires obtaining a license from ARM Ltd. to design processors. It offers low power consumption and holds a high share in the embedded field, but specification changes and custom extensions are subject to license agreement restrictions.

The fundamental difference with RISC-V is that it is open source. Anyone can freely view and use the specification, and design and manufacture their own processors without licensing fees. This makes it easier for small-scale developers and startups to enter hardware development.

The main challenge at present lies in the maturity of the ecosystem. x86 and ARM have established compatibility with operating systems, development tools, and applications. Toolchains and OS support for RISC-V are improving rapidly, but there is still a gap in commercial-scale track records.

Advantages and Disadvantages of RISC-V

The main advantages of adopting RISC-V are summarized below.

First, the cost reduction effect is remarkable. Since no licensing fees are required, fixed costs for chip design can be significantly reduced. This makes processor development possible even for organizations and startups with limited R&D budgets.

Second, there is design flexibility. Since extension instructions can be freely added, processors optimized for specific applications (such as AI inference, cryptographic decryption, and signal processing) can be designed. It becomes easier to design a general-purpose core combined with dedicated accelerators.

Third, there is transparency and reliability. Because the specification is fully disclosed, the operation of the hardware can be understood in detail. Security audits and reliability evaluations are easier, and adoption is being considered even in fields such as national defense and space development.

On the other hand, there are also current disadvantages.

First, the toolchain is not yet fully developed. Compared to proprietary instruction sets, development environments such as commercial-grade compilers, debuggers, and simulators are still limited. In particular, the maturity of tools that perform advanced optimization is insufficient.

Second, there is the performance perspective. In general-purpose computing performance, it is not easy to achieve parity with the latest high-end x86 or ARM cores. It is necessary to effectively utilize extension instructions and design tailored to specific applications.

Third, there is the state of standardization. Some extension instructions are not yet considered stable specifications. There is a risk that specifications may change during the design process, so careful consideration is required for long-term product development plans.

Real-World Use Cases and Implementation in

the Field

Actual applications of RISC-V are described by field.

In the embedded systems field, adoption is progressing in home appliances, automotive ECUs (electronic control units), and controllers for industrial robots. Low power consumption and customizability are highly valued, and cost reduction effects directly translate into profits.

For IoT (Internet of Things) devices, RISC-V is suitable in scenarios requiring energy-saving performance, such as environmental sensor nodes and wearable devices. Small-scale chip designs are possible, and battery life can be extended.

In the research and education field, it is used as teaching material in university computer architecture courses. Because students can learn the entire flow from actual hardware design to implementation, the educational effectiveness is high.

In the edge computing field, it is used in devices that execute AI inference and data preprocessing locally. By utilizing vector extension instructions, specific mathematical operations can be accelerated.

In emerging markets, particularly in China and India, RISC-V is attracting attention as a strategy to reduce dependence on foreign technology. Multiple domestic companies have developed RISC-V-based processors, and commercial shipments have begun.

Latest Trends and Future Outlook

Trends related to RISC-V have accelerated rapidly since 2023.

In 2023, T-Head (a subsidiary of Alibaba) began mass production of the RISC-V-based server processor “C910.” Numerous patches for the Linux kernel have also been submitted, and practical use in the server market is becoming increasingly realistic.

In Europe, the “European Processor Initiative” is advancing development plans for next-generation processors adopting RISC-V. In the automotive field, companies such as Continental and Bosch are considering adopting RISC-V cores, and use in in-vehicle systems is expanding.

In Japan, the “RISC-V Japan” consortium was established in 2023, with automotive and embedded equipment manufacturers participating. Utilization in the domestic semiconductor supply chain is expected.

In 2024, NVIDIA announced that it had adopted RISC-V cores for the control cores of its GPUs. This resulted in wide recognition of RISC-V’s reliability and versatility.

Operating system support is also progressing. FreeBSD and Zephyr RTOS, among others, have officially added RISC-V support, and the development foundation is being established. The growth of the ecosystem is expected to accelerate even further.

Editorial Opinion

When evaluating RISC-V, it is necessary to make judgments based on the scale of the development project and the product lifecycle. For specific applications such as embedded systems and IoT, RISC-V’s cost advantages and flexibility directly translate into benefits. On the other hand, for general-purpose servers and PCs, ecosystem maturity and performance are of greater importance. If the development team is small, existing options such as ARM should also be considered.

In the field, the proper use of RISC-V’s extension instructions is an important pitfall. While extensions are freely possible in principle, overusing proprietary extensions can compromise compatibility with the existing software ecosystem. It is essential to clarify the scope of extension instructions at the design stage and consider future standardization directions.

Over the next one to three years, RISC-V is expected to expand its scope from the embedded market to the server market. In particular, chips equipped with dedicated instructions are likely to appear in AI inference and edge computing. As the ecosystem matures, competition with x86 and ARM will intensify, and market diversification will accelerate.

References

• RISC-V International Official Website (https://riscv.org/)
• University of California, Berkeley RISC-V Project (https://riscv.org/academic/)
• “The RISC-V Reader: An Open Architecture Atlas” by David Patterson and Andrew Waterman
• IEEE Spectrum: RISC-V Related Articles (https://spectrum.ieee.org/tags/risc-v)
• T-Head Official Website (https://www.t-head.com/)